资源列表
Verilog_02
- Verilog Golden Reference Guide
VerilogHDL_-03
- VerilogHDL a guide to digital design and synthesis
Verilog_04
- Verilog code style代码编写规范-verilog code style
Verilog_05
- Verilog HDL synthesis 综合实用教程-Verilog HDL synthesis a practical primer
S2C-Dual-Virtex-6
- S2C Dual Virtex-6 TAI LM datasheet
sdr
- SDR控制器的设计和仿真testbench-the controller of SDR memory,and the simulation of testbench
sdram_vhdl
- SDR 控制器，采用VHDL语言设计。初学者可以学习和借鉴。-the controller of sdr with VHEL
UART-VHDL-Example-Code-for-an-FPGA-or-ASIC-from-n
- UART code using VHDL for FPGA or ASIC
adaptive_cut
- FPGA自适应截位代码，用verilog写的-FPGA adaptive cut-digit code, written by verilog
mat_det
- 基于FPGA的3阶矩阵求行列式的verilog代码-FPGA-based third-order matrix determinant verilog code
Gen_R
- FPGA中将用采样点产生相关矩阵R的verilog代码-FPGA will generate correlation matrix R verilog code with the sampling points
u_channel_correction
- 基于FPGA的通道不一致性校正的verilog代码-FPGA-based channel inconsistency correction verilog code