资源列表
miaobiao
- EDA--miaobiao design-vhdl----miaobiao design
i2c_code
- I2C protocol which as been verified and tested using testbench
viterbideoderupdated
- Viterbi decoder source code is in verilog with CRCv-Viterbi decoder source code is in verilog with CRCv
Encrypt_Decrypt(DES)_Verilog
- Encrypt and decrypt DES algorithm in verilog
picture_vga
- 基于FPGA的VGA接口程序设计（小绿人快跑）-VGA interface program design based on FPGA (little green men run)
uart_rx_module24
- UART serial interface communication based on FPGA, this modular by receiving PC serial port data (8), converted into parallel 24 data output
DDS
- 基于FPGA的DDS波形发生模块，频率相位可调-Module based on FPGA DDS waveform，Adjustable frequency phase
led0
- 一个最简单的LED实验程序，供新人学习和参考，简单易懂-One of the most simple LED the experimental program, for newcomers to learn and reference, easy to understand
spi
- 基于FPGA的spi通讯模块（16位数据输出）-Spi communication module based on FPGA (16 bit data output)
LM75-TTT
- VHDL 实现的 LM75 的控制器 读取 LM75数据-VHDL realization of LM75 LM75 controller read data
fp1-40-1_1
- fpga任意频率输出，精度《=2 ，串口控制分频系数，从50hz-51.2k精确分频，其中还包括小数点的处理。 通信部分：波特率处理模块、数据接受模块、数据校验及解码模块 分频部分：altpll锁相环模块，分频数计算模块、小数0.5检验模块、分频模块 -fpga any frequency output accuracy " = 2 , serial control division factor, from 50hz-51.2k precision divider, whi
delay
- VHDL代码，源用与两路DDS之间的相位差，现可用于产生相位差可编程的1m时钟，精度可精确到0.01分。输出两路时钟，带起始控制位-VHDL code, source with the phase difference between the two DDS, can now be used to produce 1m phase programmable clock accuracy can be accurate to 0.01 points. Output two clocks with