资源列表
f_adder
- 利用VHDL的语言，实现考虑进位的全加器，该程序带中的加法器带有使能端，可以更好地实现所需功能。-Using VHDL language to achieve considering the carry bit full adder, the program with the adder with Enable, can better achieve the desired function.
CNT4_S
- 该程序为运用VHDL语言，基于FPGA平台实现的一个四进制的计数器。-The program for the use of VHDL language, FPGA-based platforms to achieve a quaternary counter.
LPM_ROM
- 该程序是一个正弦信号发生器，信号的频率可控，利用FPGA的ROM，可以对正弦信号的相应电位进行查表，具体电位的地址由计数器得到。-The program is a sinusoidal signal generator, the frequency of the signal controlled by the FPGA ROM, may be a sinusoidal signal corresponding to the potential of the table, the address
M130095EC
- vhdl code for uart. data tx from pc to fpga nd vice versa
Program
- 用ALTERA公司的FPGA写的网卡W5300程序-W5300 in fpga
how_to_create_nios_II_application
- Nios II basic development tutorial project
verilog-source-codes
- the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
MY_DCM
- DCM测试模块，带有仿真文件和仿真结果，对于初学者有一定的参考价值-DCM test module, and simulation results with the simulation files for beginners have some reference value
SDI
- SDI显示模块，亲测，能够显示8*Block的黑白渐变图像，分片率1920*1080P/30F-SDI display module, pro-test, can display 8* Block black and white gradient image, fragmentation rate of 1920* 1080P/30F
KEYDIS
- 硬件调试出来了，比较靠谱，文件挺简单的，希望有所帮助- Hardware debugging, comparison, the file is quite simple
EX4V1.1
- 该设计是基于Verilog HDL的秒表。此设计是在Altera的Cyclone II系列的FPGA上验证过了。能够实现精确计时。-This design is a stopwatch based on the Verilog HDL. And it has been verified on the platform of Cyclone II s FPGA of Altera. Finally it can achieve accurate timing.
PADS-Layout
- PADS Layout四层板设置教程,对于入门学PADS Layout四层板很有帮助。-PADS Layout four-layer board set tutorial, learn PADS Layout for entry four-layer board is helpful.