资源列表
i2c_slave
- I2c slave 16 bit data verilog 代码-i2c slave verilog code
LAB7_1
- LAB 7 VERILOG DE2-115
LAB7_3
- lab7 part 3 verilog de2-115
async.v
- verilog code for UART module
SIN_GNT
- LPM_ROM定制。简单的正弦波发生器。 Verilog HDL语言设计。 EP4CE15F17C18N实测可用。-LPM_ROM customization. Simple sine wave generator. Verilog HDL designs. EP4CE15F17C18N measurement available.
Verilog.HDL
- <精通Verilog.HDL语言编程_源码>-< Proficient Verilog.HDL source programming language _>
LCD1602
- 液晶1602的FPGA驱动程序，可实现16x2的字符显示-1602 FPGA LCD drivers, enabling 16x2 character display
Verilog
- 书本Verilog设计与验证的书本源码，望能帮助到有需要的人！-Books books Verilog design and verification code, hope to help the people in need!
lcd5110-frequency
- 用nakio 5110显示波形的Verilog程序！主要学习液晶的Verilog驱动！-Program with nakio 5110 Verilog waveform display! The main study of Verilog LCD driver!
PCI9054_Interface
- PCI9054接口控制逻辑,带有DMA功能和普通寄存器功能-PCI9054 Interface
ADS1252
- 内容为运用FPGA驱动ADS1252的工程文件，时钟频率为10M,内部使用了锁相环，可以自行调节采样频率。-FPGA-driven content for use ADS1252 project file, the clock frequency is 10M, internal use of the phase-locked loop, you can adjust their own sampling frequency.
M-series-digital-signal
- 第一路用于产生一个10Mbps的M序列，第二路产生10Kbps到100Kbps的M序列，数据率可以按10Kbps步进。-The first way to generate a sequence of M 10Mbps, the second way to produce 10Kbps to 100Kbps M-sequence data rate can 10Kbps steps.