资源列表
jiaotongdeng
- 用VHDL做的一个交通灯的实验，这个程序的主要功能是：有8个灯，主路和支路分别增加了转弯的灯；有救护车，当救护车按键为高电平时，产生救护车中断，主路和支路红灯亮。同时数码管在当前计数值和全0之间循环显示；有喇叭voice；-Use VHDL to do a traffic light experiment, the main functions of this program: There are eight lights, the main road and slip roads increa
Clock_generator
- Verilog source code for a clock generator
DigitadesignCPLD_VHDL
- Digital Design with CPLD and VHDL
44vhdl
- 44个vhdl设计实例，有兴趣的可以看看，希望能帮助大家-44 vhdl design examples are interested can look at, hoping to help people
VHDLReferenceManual
- ＶＨＤＬ语言参考手册，希望能帮助大家学习和设计-VHDL Language Reference Manual, hoping to help people learn and Design
NewFolder
- these are some verilog codes
zhedashumo
- 浙大数学建模课件，很不错的，希望对你们有用-zhe da shu mo kejian
learnVHDL
- 哈尔滨工程大学的VDHL课件，希望能更好地帮助大家学习VHDL语言-Harbin Engineering University of VDHL courseware, hoping to better help them to learn VHDL language
FREQTEST.tar
- VHDL写的16进制显示数字频率计，用8位数码管显示-16 hexadecimal display digital frequency meter VHDL
manchesterbyxilinx
- 曼彻斯特编解码的实现（Verilog）,包含有测试文件。-manchester encode and decode with verilog，Test File is included。
BUIW_framework
- 这是一篇关于buiw的框架说明文档，很值得学习。-It display buiw framework！
Verilog
- VERILOG语言的学习，更好的运用CPLD，FPGA-VERILOG language learning, better use of CPLD, FPGA