资源列表
shuzizhongcankaoverilog
- 这是我设计数字钟参考资料，还不错，适合初级verilog选手参考使用，一定得先看懂了一些设计，自己上手才会快。-This is my digital clock reference design, but also good for junior players for reference verilog, must first understand some of the design, their own will get started soon.
div_res
- 这是一个用VERILOG实现的除法的指令，用状态机实现的，希望对大家有用-THIS IS A CODE FOR DIV OF VERILOG。ITS USEFUL...
ADC0809
- 用状态机描写的ADC0809的驱动程序，希望对于刚接触状态机的新手有所帮组-IT IS USEFUL.....
dds
- 这是用VERILOG描写的一个DDS的实例，涉及到一些lpm的运用希望对大家有用-it‘s useful。
LPC2DDR2
- Module Function Descr iption: This module allows a SPI ROM to be used in a LX/CS5536 system. Details are below: 1.Provide a memory window to the SPI EPROM at FFF80000h-FFFFFFFFh (512KB). 2.Provide an interface to the SPI bus to allow the
SwitchCheck
- 一个通用的SPI程序,由VERILOG语言编写。时钟由控制机提供，可以修改SPI的发送数据位数。-a SPI codes
yimaqi
- 四输入译码器，转换成为十六进制共阴极数码管显示，从0~F.-4 input decoder, be converted into hexadecimal common cathode LED display, from 0 ~ F.
monitertest
- 显示器图像图纹程序 实现3种图像显示途径 调试成功能够实现-Display image Patterns program to achieve three kinds of image display means of debugging can be achieved successfully
single_cycle_16bit_computer
- This single cycle 16-bit computer with testbenches written in Verilog. It shows a result based on the instruction memory. I also included documents about the structure of the single cycle computer-This is single cycle 16-bit computer with testben
ise_11[1].3_licgen
- ise11.3的，请用来学习又没有钱的朋友使用，不要外传，谢谢！-ise11.3, please no money is used to study the use of a friend, not rumor, thank you!
Project_WorkSpace
- The code i have written is for the patent designed by Jay Hartvigsen, Tony Cheng, Eric Hoang and Buddy Broeker "JTAG/DEBUG INTERFACE". This is meant for the purpose of interfacing the controller to debug its core,this code is working fine n very so
Bin2Grey
- 一个用Verilog语言实现的二进制码到BCD码的一种转换方法的实现。包含工程文件和实现文档。-Verilog language implementation with a binary code to BCD code conversion method as a realization. And the achievement of the document contains the project file.