资源列表
XilinxExample.tar
- xilinx software to demonstrate vhdl programming
serial_input_parallel_output_module
- 有一批数据并行输入，位宽为4，输入的时钟频率是20MHz，模块的功能是对这些数据进行并串转换。它每收满6个数据（一个包），就对这6个数据进行处理，将这6个数据按照一定的顺序串行输出，输出的时钟频率是80MHz-serial input parallel output
Number_Lock
- 数字密码锁，能进行10位密码的加锁与解锁。 -Number of locks that can be 10-bit password, locking and unlocking. Number of locks that can be 10-bit password, locking and unlocking.
FPGA_cy7c68013
- 本工程包括FPGA程序和CY7C68013固件程序。 上位机程序通过EZ-USB CONTROL PANNEL 来测试。-The works include the FPGA programs and CY7C68013 firmware. Host computer procedure EZ-USB CONTROL PANNEL to test.
FPGA_double_DDS
- High performance double sinusoidal oscillator having frequency and phase programmable. -High performance double sinusoidal oscillator having frequency and phase programmable.
code
- 用dff方法实现二分频，行为描述实现二分频，二分频，投票代码，有限状态机-Dff method used to achieve two-way, behavioral descr iptions to achieve two-way, two-way, voting codes, finite state machine
project
- 利用VHDL实现三个简单的程序：BCD加法器；ALU算术逻辑单元；简单密码锁设计，具有输入密码和数据比较两种功能，由M决定是写入还是开锁。而数据写入是采用列地址与输入数相结合的的方法，存入初始密码；开锁时，密码以输入，再输入的数据逐个与输入的一组数据比较，完全吻合则开锁。-The use of VHDL to accomplish three simple procedures: BCD adder ALU arithmetic logic unit simple lock design,
projiect
- 简单数字系统的系统级设计，完成E1clk 时钟1/32 分频产生64K 时钟的设计-A simple system-level design of digital systems to complete E1clk clock 1/32 min 64K clock frequency generated design
VerilogHDL
- 很不错的一本书，学习verilog hdl 必备-A very good book to learn verilog hdl essential ~ ~
uart
- VHDL编写的异步输入输出接口控制程序 从网易博客上下的-VHDL write asynchronous input and output interfaces control the process from top to bottom Netease blog
ModelSimdeyongfa
- 这是ModelSim软件建立工程、仿真的简单快捷方法，是我的总结，希望可以帮助想要使用ModelSim做仿真的朋友-This is the ModelSim software to establish engineering, simulation of a simple and speedy way is my conclusion, I hope to help do you want to use the ModelSim simulation of a friend
trafficsheji
- 交通设计的verilog程序，我的课程设计就是参考这个的-Traffic design verilog procedure, my course design is a reference to this in