资源列表
sram
- sram vhdl code. Very helpful
Verilog_HDl_Code
- 《精通Verilog HDL语言编程》中的Verilog实例源码-Verilog HDL Code
CFO_Correction
- 载波频率同步Verilog程序 基于xilinx ise 实现-Carrier frequency synchronization Verilog program is based on xilinx ise to achieve
modelsim8255
- this a programmed VHDL source for intel 8255,I have made some process in some details,I hope your all will like it!-this is a programmed VHDL source for intel 8255,I have made some process in some details,I hope your all will like it!
traffic_light
- this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit]. -this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit].
xapp199(E)
- 真的很经典 的VHDL类的激励文件的编写，是初学的人最好用的资料。-SO GOOD
clock
- 数字时钟的verilog程序，在alteral ep2c5t144调试成功-Digital clock verilog program
3.3
- 编码-译码显示电路 输入按键0-9 用数码管显示输入数据-Encoding- decoding display circuit input keys 0-9 shows the input data with a digital control
shuzizhongsheji
- s1. 所设计数字钟具有“时”、“分”、“秒”的十进制数字显示（小时从00～23）。 2. 可以进行手动校时、校分功能。 3. 能进行整点报时。从59分51秒开始每隔2秒钟连续发出四次低音“嘟。嘟、嘟、嘟”，，最后一次发出高音“嗒”。此信号响起时即达整点。 -you can see see
UART_TX
- 串口通行驱动，波特率自行更改，可以升级为自动使用于不同的接口-Serial port access driver, change the baud rate on their own, you can upgrade automatically use in different interfaces
verilog_300examples
- verilog的300个例子，很全的，我自己都试过-verilog 300 examples, it is full, and I have tried