资源列表
Crossover-design
- 在Altera DE2-70的开发板上实现分频计设计。-In the Altera DE2-70 development board to achieve crossover meter designs.
frequency-meter-design
- 在Altera DE2-70的开发板上实现频率计设计。-Achieve frequency meter design Altera DE2-70 development board.
crc_peripheral32
- 附件是32位循环冗余校验码的硬件语言（v语言）实现。-Attached is a hardware language 32 cyclic redundancy check code (v language) implementation.
Verilog-example
- Verilog 例子 说明，值得借鉴，学习Verilog的新手过来看看吧-Verilog example
cic3s200
- cic抽取滤波器,用于采样率远高于信号频率的情况下。-cic filter
vga789
- 这是一个Verilog的文件。可以实现在液晶显示屏山显示一副图像。-This is a Verilog file. Can display an image on the LCD Hill.
halfadder.v.tar
- Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...
fulladder.tar
- Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
basicgates
- Verilog Code for Basic Gates implementation with testbench-Verilog Code for Basic Gates implementation with testbench..
mux4_1
- Verilog Code for 4*1 Multiplexer with testbench file-Verilog Code for 4*1 Multiplexer with testbench file...
8bit_decoder
- Verilog code for 3*8 Decoder Circuit with testbench file-Verilog code for 3*8 Decoder Circuit with testbench file....
UART_RX
- 这是借鉴别人的带有FIFO的Verilog代码分享给大家，共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together