资源列表
fenpin
- 关于FPGA的分频程序，使用VHDL书写，可用于模块化编程-fractional frequency
shuzishizhong
- FPGA代码，数字时钟，可调小时，分钟，秒钟，调节时闪烁-digital clock
seg
- 四位一体数码管显示，实现数码管动态显示。已经测试，很好用！-Four digital tube display, realize the dynamic display of digital tube.Already test, very good!
i2s_latest
- Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL De
my_uart2
- 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Sum
vga256
- 这是一个Verilog的VGA程序，可以再显示屏上显示8种颜色-This is a VGA-Verilog procedures can be shown on the display 8 colors
sp605_pcie_13.2
- 基于FPGA，pcie开发的源码程序，已经经过测试，上传来给其他爱好者学习交流。- input user_clk, input user_reset, input user_lnk_up, // Tx input [5:0] tx_buf_av, input tx_cfg_req, output tx_cfg_gnt,
EDK_adv212
- 控制ADV212 压缩的源代码 使用xilinx edk开发环境-adv 212 controller, using xilinx edk
LCD12864
- 该程序用于CPLD控制12864显示,显示内容见http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8734321251-The program is used to control CPLD 12864，link:http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8734321251 to view
lcd1602
- 该程序通过CPLD控制1602显示，显示效果见http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8732102150-CPLD to control the program by 1602, the display see http://zhuxiangqing.blog.163.com/album/# m = 2 & aid = 264724219 & pid = 8732102150
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code
hardware-qpskmodulate1
- 采用硬件描述语言verilog进行QPSK变换的实现的代码- Using hardware descr iption languages Verilog implementation of QPSK converter code