资源列表
vdhl_smg
- 完整代码工程，实现74HC595驱动数码管显示，利用VHDL实现；-Complete code project, the realization of 74 hc595 are needed to drive the digital tube display, using VHDL realization
Our_MIPS_CPU
- 基于MIPS架构的CPU设计，含有完整程序代码，及各模块实现及仿真程序！-CPU design based on MIPS architecture, contains a complete code, and the realization of each module and the simulation program
PWM_LED
- 基于DE2_70平台，编写nios软核c代码，控制流水灯，硬件实现验证通过，适合入门-Based DE2_70 platform, written nios soft core c code, control water lights, verified by hardware implementation, suitable for entry
SW_LCD1602_irq
- SW_LCD1602_irq是nios中实现按键中断以及lcd1602显示-SW_LCD1602_irq is implemented nios interrupt button and display lcd1602
UART_DMA
- UART_DMA的方法是使用nios实现UART方式实现DMA传输，在硬件平台上通过验证实现-UART_DMA way is to use uart dma transfer nios implemented in the hardware platform validated by
SW_HEX
- SW_HEX.rar是verilog编写的按键计数功能源代码-SW_HEX.rar is written in verilog achieve counting function keys
DE2_70_NET_UART_DMA
- 采用NIOS编写c代码实现dma传输，加入dma9000网络传输功能-Write c code using NIOS dma transfer, adding dma9000 network transmission function
ad7606
- ADC7606的驱动代码，采用verilog实现-ADC7606 driver code, using Verilog to achieve
16_clk_generator
- 简单的任意分频源码,可以通过调节参量改变输出频率-Simply divide any source, the output frequency can be changed by adjusting the parameters
LED
- QuartusII 9下的LED灯示例，很简单的例子，可以直接运行-The sample of LED of quartus II 9.0 with the language of Verilog
Simple_Logic_Continue
- quartusII 9编写的74161模块，简单的例子，可以直接运行-The module 74161 with the language of verilog
XC2C
- 基于FPGA的8路心电数据采集，发送给MSP430.-FPGA-based 8-channel ECG data acquisition, send MSP430.