资源列表
88dianzhen
- 用VHDL语言编写的8*8点阵显示“北京08”的程序。可以用FPGA实现。可将程序当中的“北京08”改成别的汉字显示。-VHDL language using 8* 8 dot matrix display, " Beijing 08" procedures. FPGA implementation can be used. Procedures which could be the " Beijing 08" be changed to show the o
wannianli
- 数字万年历，可显示年月日，时分，具有闰年功能。VHDL语言编写，利用DE2平台实现。-Digital calendar, date, time, with a leap year. VHDL language using DE2 platform.
61EDA_D158
- 关于VGA显示接口的一些代码可以下载
1(3)
- 确实是 介绍synplicity.的一本好书-synplicity.synplicity.
pinlvji
- 用VHDL语言编写的频率计，在FPGA上使用，已验证，全工程文件-In the frequency of the VHDL language, on the FPGA has been verified, the whole project file
VGA_FPGA_v8_08
- VGA0808矩阵FPGA代码（Verilog HDL语言）-VGA0808 matrix FPGA code (Verilog HDL language)
TrafficLight
- 用verilog写的一个智能交通信号灯的源码-a traffic light simulator built with verilog
verilog
- verilog 常用模块，包含设计模块和测试模块，如有ram, lifo等-verilog useful blocks
SeniorFPGADesign
- 清华大学电子工程系的FPGA高级设计技巧教程-Department of Electronic Engineering of Tsinghua University, Senior FPGA Design Basics
t1
- 带清零和重置功能的十进制计数器，可以用LED灯显示结果-Cleared and reset with the decimal counter, can use LED lights display the results
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a pre
music
- 以vhdl 語言利用nios編寫的音樂控制範例.altera de2板實測可用-Vhdl language used to write the music control nios sample. Altera de2 board can be measured