资源列表
cout60
- 用VHDL语言编写的60进制计数器，初学者使用-VHDL language with the 60 binary counter, for beginners to use
sheji
- 本科毕设，基于cpld的光栅信号处理，包含源代码和模块框图-Undergraduate Bi is located, based on cpld grating signal processing, including source code and block diagram
SFIFO
- 可以实现任意位的同步FIFO的verilog实现-the verilog code of a common SFIFO
cfft
- 用verilog语言编写的基4FFT，采用CORDIC算法实现的，仿真过，结果很好！-I use verilog language to design a FFT base 4,and use CORDIC arithmetic to achieve this. last , I test it, it looks very good
freq_divider
- 8bit分频器，最高256*2=512 分频，使用emacs编写源文件，iverilog仿真通过-8bit divider, the maximum 256* 2 = 512 min frequency, use emacs to prepare source file, iverilog simulation success
trigger
- D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
jitter_eliminate
- verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted
rotate_switch
- 双触点旋转开关verilog驱动，内置消抖模块。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-Double-contact rotary switch verilog drive, built-in modules eliminate shaking. Prepared source files using the emacs, iverilog simulation adopted, within the simulation images png screen
DDR_controller_verilog
- ddr的控制程序，用verilog实现的，非常的具体。-ddr
FPGA_Design_Introduction
- 电子工程师创新设计必备宝典系列之FPGA开发全攻略-Innovative design of electronics engineers must-Collection Series FPGA development all Gonglue
multiplier_booths
- a verilog code for booths multiplier has been uploaded, simple architecture.
dualelevatorcontroller
- Verilog code for dual elevator controller. contains code for the controller of dual elevator for a building with 4 floors. the test bench is also present