资源列表
jtag_uart_0
- jatag在nios环境下的接口代码，可在ISE或quartus下完成调试-Nios jatag environment in the interface code, can be accomplished under the ISE or Quartus debugging
uart
- 自己编写的UART代码，希望大家查考，如果有什么建议请指出。-UART code I have written, I hope you diligently, and if you have any suggestions, please point out.
pingpongf16
- 16个pingpong像屏幕四周弹去，遇到边框则90度反弹，一直重复下去-sixteen pingpong in the screen.
DS28E01
- 用verilog语言实现加密芯片DS28E01的调用操作命令。-Using Verilog language to achieve the encryption chip DS28E01 call operation commands.
test_bram
- 用FPGA实现bram测试，sparden 3s 250e-With the FPGA to achieve bram test, sparden 3s 250e
rle
- 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
VHDL源代码1
- VHDL源代码包-VHDL source code
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, d
1602
- 关于lcd1602显示控制，作用于FPGA显示一连串字符串代码。-the control of lcd 1602 use the vhdl language
用cpld实现曼彻斯特编码
- 用cpld实现曼彻斯特编码 用verilog HDL进行曼彻斯特编码，用于通信中-cpld achieve with Manchester encoding with Verilog HDL Manchester encoding. for Communication
shijian
- 简易电子时钟，可同时有数码管和lcd上显示时间-Simple electronic clock, can simultaneously display the time on the digital tube and lcd
Actel_get_started_fusion
- Actel tipical get started project adapted for Fusion devices.