资源列表
ourdev_636633GLRJ7O
- 基于Verilog的格雷码,运用二进制与他的关系进行求解-the implemation of geleima based on verilog
jtag_uart
- SOPC jtag uart 系统集成编译的IP核-Jtag-uart IP core in SOPC
Stepper motor
- 步进电机基于PWM的控制，可以实现起动，制动，调速等等的功能，着实是初学者的一大福音-PWM-based control of stepper motor can be achieved starting, braking, speed, and so the function is, indeed, a boon for beginners
FdplllzipP
- ＦＰＧＡ实现全数字锁相环，运用硬件描述评议议verilog HDL，顶层文件ＤＰＬＬ．Ｖ -FPGA implementation of DPLL, the use of hardware descr iption council meeting Verilog HDL top-level file DPLL is. V
x95288x
- VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only
vhdl_TRAFFIC
- 十字路口 ，交通灯， VHDL ， EDA，用MAX+PLUS2运行，-Intersections, traffic lights, VHDL, EDA, with the MAX+ PLUS2 run
filter_stage3
- 滤波器，24位的，可综合代码，易懂好理解-Filters, 24-bit, and can be integrated code, to understand better understanding
i2s_latest
- Details Name: i2s Created: Mar 22, 2004 Updated: Jan 10, 2014 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other project properties Category: Communication controller Language: VHDL De
uart
- 基于spartan3e的串口驱动程序，使用verilog编写-Based spartan3e serial driver, written using the verilog
vhdl
- vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。-vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.
code
- this a muti cycle mips code that it can do mutiply,add,sub,xor,beq,bne,slt,sltu,ori,xori and... and it take address and data and then operate on them.-this is a muti cycle mips code that it can do mutiply,add,sub,xor,beq,bne,slt,sltu,ori,xori and...
1024fft
- 使用vhdl实现的1024点的FFT算法-Using vhdl implementation of the 1024-point FFT algorithm