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资源列表
FIFO_8_8
- FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
p21
- mips pipeline的源代码，很简洁，很适合新手使用。大学三年级的必修课。-mips pipeline source code, very simple, very suitable for beginners to use. University of grade three compulsory.
fm25h20
- spi接口，DSP发送数据，FPGA缓存起来，然后通过spi口写进fm25h20芯片里面-Spi interface, DSP send data, FPGA, and then through the spi cache up mouth written into fm25h20 chip inside
ALU
- 8位ALU的设计，学习使用vhdl元件和包集设计-8-bit ALU design, learning to use vhdl components and package design
SPI
- SPI串行总线接口的VERILOG实现的源代码-failed to translate
8b10bverilog
- 基于verilogHDL语言的8b10通信变换。-verilog 8b10b
Baseband-code-generator-program
- 基带码发生器 功能：基于VHDL硬件描述语言，产生常用基带码-Baseband code generator program use IEEE.STD_LOGIC_1164.ALL use IEEE.STD_LOGIC_ARITH.ALL use IEEE.STD_LOGIC_UNSIGNED.ALL
can
- can bus is used to transfer data faster and also power saving-can bus is used to transfer data faster and also power saving............
5-Source-code
- 5 Source code for computer ports 1- ps2 2-ps2 test 3-rs232 4-rs232 test 5-Fulladder for counter in clock divider
lcdvhdl
- This LCD controler write in vhdl. Use HD44350A01 controler lcd-This is LCD controler write in vhdl. Use HD44350A01 controler lcd
nand_flash_ctl
- FPGA flash 控制读写程序 与mcu相连-FPGA flash control is connected to read and write procedures and mcu
lift_control
- 用verilog语言编写的一个100层电梯控制系统。-Verilog language with a 100 floor elevator control system.