资源列表
CPU
- mips系列，CPU的Verilog语言设计，自己写的-mips series, CPU of the Verilog language design, to write their own
FPGAdezizhixingSPWMboChengXu
- 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit
4_memory_access
- Risc processor:- memory acce-Risc processor:- memory access
8_bit_adder
- Implementation of an 8-bit adder.
usefulUART
- UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA器件设计与实现UART。 -UART is a widely used serial data communication circuits. This design includes UART transmitter, receiver and baud rate generator. Design and Application of EDA technology, ba
PCI
- PCI总线仲裁参考设计Verilog代码，包括一些说明文件-PCI bus arbitration reference design Verilog code, including some documentation
fpgavhdldaima
- 用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
CascadeCounter
- 一个基于Spartan3E的级联计数器，通过验证可用-A cascade of counter-based Spartan3E, available through the validation
Processor_alu
- this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
apb_slave_latest.tar
- APB slave master uding verilog
Adder4
- 本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的-The design is to design a full adder 4 content, is one of four full adder in series from the
lcd
- c8051F单片机液晶显示与驱动程序，开发环境为keil-c8051F chip liquid crystal display and driver development environment for keil