资源列表
verilog_lcd
- 在Quartus ii 环境中实现了LCD模块的控制功能，程序由verilog hdl 语言描述，经测试，该模块功能与预期一致。-In Quartus ii environment to achieve the control functions of the LCD module, the program described by the verilog hdl language, tested, this module functions in line with expectations.
verilog_ps2
- 在Quartus ii 环境中实现了PS2模块的控制功能，程序由verilog hdl 语言描述，经测试，该模块功能与预期一致。-In Quartus ii environment to achieve the PS2 module control functions, procedures described by the verilog hdl language, tested, this module functions in line with expectations.
verilog_vga
- 在quartus ii开发环境中实现了vga模块的控制功能，经测试，该模块能产生正确地时序，功能与预期功能一致。-In quartus ii development environment to achieve the vga module control functions have been tested, the module can generate correct timing, functionality consistent with the intended function.
10_uart
- 在quartus ii开发环境中实现了uart串口通信模块的控制功能，经测试，该模块能产生正确地时序，功能与预期功能一致。-In quartus ii development environment to achieve the uart serial communication module control functions have been tested, the module can generate correct timing, functionality consistent w
jtag
- verilog语言编写的jtag（边界扫描模块），初学的时候可以-verilog language jtag (boundary scan module), a novice when you can look
fifo
- 同步fifo，使用ISE13.4 V5器件 速度550MHz-Synchronous fifo, use ISE13.4 V5 device speed 550MHz
usbfifo
- 一种USBfifo的传输方式。控制数据向USB端点中传输数据，-A transfor way for USB，control the data to endpoint.
DoubleRoad
- 用VHDL编写的FPGA程序，运行在ISE中，仿真通过，设计一种CCD的采集方案-The FPGA program written in VHDL, run in the ISE, simulation, design a kind of CCD acquisition scheme
ADC
- VHDL编写的同步时序逻辑程序，实现AD的数据采集，已经 通过仿真。
vhdldelay
- 用VHDL编写的一个软件延迟，比较好用，可以自己设定延迟时间。-Use VHDL to write a software delay, use, can set the delay time.
fourroadccd
- 一种CCD采集模式，思路采集，每路12位，思路同时实现48位高速传输。-A CCD acquisition mode, collection, each road 12, thinking the 48 high-speed transmission at the same time.
ram_data
- 一个RAM与USB相连，测试数据传输，使用USB3.0开发板已经测试成功。-A RAM are connected to the USB, the test data transmission, use the start development board has been tested successfully.