资源列表
Dct_verilog
- 采用verilog hdl 语言实现整形dct算法，设计合理，算法简单，是红色逻辑开发板试验程序，值得一看。
i2c_master_model
- i2c仿真model,可用于整体的FPGA仿真系统,用于i2c slave 设计的正确验证-i2c simulation model, the FPGA can be used for the whole simulation system designed for the proper verification i2c slave
Stepper-motor-VHDL
- 步进电机定位控制系统VHDL程序与仿真，想要的快来下吧～-Stepper motor positioning control system and simulation VHDL program, want you ~ Come
motor-VHDL
- 步进电机定位控制系统，VHDL程序与仿真-Stepper motor positioning control system procedures and VHDL simulation
matricode
- 矩阵键盘扫面程序。还不错，亲自试过，大家捧场呀！-Matrix keyboard sweep program. Is good
Timing-
- 利用verilog设计的停车场中的计数器计时器和计费器，完成智能管理效果-Use the counter timer and meter parking lot in the Verilog design, intelligent management
dianziqin
- vb编写的电子琴，仿真实电子琴操作界面，包含与FPGA串口通信的功能。-vb prepared organ, electric piano emulation interface is included with the FPGA serial communication functions.
BuJinDianJiKongZhi
- 步进电机定位控制系统VHDL程序与仿真 关键词： 1激磁方式的选择开关 2步进角的倍数设定输入 3步进电机状态输出-stepping motor
AD1407
- 介绍关于AD1407的VGA显示功能，包括4个VHDL文件，和一个管脚文件-Introduced on the AD1407 VGA display features, including four VHDL files, and a pin file
89_full_adder
- full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合
lcd
- 利用FPGA驱动LCD显示中文字符的VHDL程序-Use of FPGA-driven LCD display Chinese characters of the VHDL program
Timer
- 嵌入式系统的单片集成定时器的Verilog实现。可实现多种配置模式，可作为通用的定时器设计模板-This is a standed timer for an SOC design.It can realize multible function need to design an micro process circut