资源列表
UART
- Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a s
SRAM
- DE2-35 SRAM简单读写VHDL源码，可以通过开发板上拨动开关输入数据，在LED上显示读写情况-DE2-35 SRAM to read and write simple VHDL source code, can input data through the development board to toggle switch, display to read and write in LED.
99mul_3
- 九九乘法表系统，ARH信号低电平时可手动输入乘数、被乘数；ARH高电平时自动生成乘数、被乘数进行99乘法计算。在自动过程中若ARH置0，则暂停当前自动生成的乘数、被乘数乘法运算，可进行外部输入，当ARH再次回到高电平1时，则返回暂停处的乘数、被乘数并继续向下运算。START信号具有一个复位重启的功能。-Nine nine multiplication table system, ARH signal in low level can be manually input multiplier, t
BitHound_SP601_1.0_
- 逻辑分析仪器代码，VHDL实现，支持100M采样速度-Logic analysis instrumentation code, VHDL implementation, support 100M sampling rate
VHDL
- 数字电路中常用的3线-8线译码器及8线-3线优先编码器的VHDL语言的功能描述-That is commonly used in digital circuit lines to 3-8 8 line to 3 line priority encoder decoder and the function of the VHDL language descr iption
FPGA_SDRAM_ReadAndWrite
- SDRAM读写控制的实现与Modelsim仿真-Implementation and Modelsim SDRAM read and write control simulation
FPGA_verilog_VGA_SimpleDemo
- FPGA初级程序,基于verilog的VGA简单接口驱动-VGA-based verilog simple interface driver
频率计
- Verilog和VHDL联合编写的频率计
2112312
- 模拟交通灯实验，实验报告 用 8255 做输出口，控制十二个发光管（4 组红绿黄灯）的亮灭，模拟十字路*通灯 管理。-Simulated traffic light experiments report To do with the 8255 output, control twelve light tube (4 groups of red, green yellow) light off, analog crossroads traffic lights Managem
frame_syn
- 通信系统中数据的传输以帧为单位，在FPGA中帧头检测是通信系统中的一部分，该程序实现了FPGA中帧头的检测。-Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in th
Mojo-Hexapod-Blob
- Verilog library for Mojo V3 FPGA development board
Verilog-HDL_01
- (Prentice) Verilog HDL--Guide to Digital Design & Synthesis (2nd.Ed.)