资源列表
irigb_quartusii
- irigb码，b码的quartus ii实现，自动产生b码。irigb code, quartus ii b code implementations, automatic code generation b.-irigb code, quartus ii b code implementations, automatic code generation b.
RS232uart(VHDL)
- rs232串口程序，包括输入和输出，vhdl实现。rs232 serial procedures, including input and output, vhdl implementation.-rs232 serial procedures, including input and output, vhdl implementation.
cunkou
- rs232，quartus完整代码，直接可使用，波特率为9600.-rs232, quartus complete code, can be used directly, 9600.
sindeshengcheng
- 正选函数的产生，由ram生成地址 verilog编写-Being elected function generates an address verilog written by ram
uartdeverilog
- uart的编写 采用verilog 绝对可以用-uart prepared using verilog can definitely use
dds_
- 基于VHDL的DDS 串口控制 ROM 文件由MATLAB生成-dds using VHDL serial control
sv-reference-doc
- systemverilog入门 用于IC验证-for test
proda_FixPt
- Fixed point code of vector multiplication
pso2
- i want VHDL coding for doing my project-i want VHDL coding for doing my project..
pso3
- i want VHDL coding for doing my project
Virtex-6-Family-Overview
- Virtex-6 Family Overview
shifter
- 用vhdl语言采用时序电路(移位寄存器)的方式实现（7，4）循环码编码器-Vhdl language used by the timing circuit (shift register) way to achieve (7,4) cyclic code encoder