资源列表
FPAG_REAL_SOURCE
- FPGA实战项目程序，适合进阶和务实的学者。值得拥有！-FPGA for advanced learner
exp5
- 用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full a
Four-quiz-Responder
- 运用VHDL语言实现四路智力竞赛抢答器。抢答器的主要功能模块是是：1、对第一抢答信号的鉴别和锁存功能；2、计分功能。3、数码显示 ；4、答题限时功能。在本设计主要讲述抢答、计分和警告的功能。-Using VHDL language quiz four Responder.Responder main function modules are: 1, for the first answer to identify and latch signal 2, scoring functio
Four-binary-adder
- 熟悉 VHDL 语言的模块化设计，了解元件例化和打包调用语句。用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then us
Count-clock-synthesis-experiments
- 练习综合设计能力，设计一个含时/分/秒的时钟，并且可以设置、清除、 12/24 小时工作模式切换。-Exercise comprehensive design capabilities, including the design of a time/minutes/seconds of the clock, and you can set, clear, 12/24 hour work mode.
GTKWave_ISim
- gtkwave simulator for fpga code
internal_reset.v
- code for internal reset in fpga
fft
- fft in verilog code for fpga
VGA
- vga显示硬件模块verilog语言编写，实现了一个动画显示，适合于初学者学习。-vga display hardware module verilog language to achieve an animated display, suitable for beginners to learn.
IO-timing-constrain-in-fpga
- 对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules
IIC
- 硬件语言verilog实现IIC控制器，严格按照IIC协议编写硬件控制器行为及代码-Hardware language verilog realize IIC controllers, written in strict accordance with IIC protocol hardware controller behavior and codeHardware language verilog realize IIC controllers, written in strict acco
MVLSI_CBP_16.-FPGA-based-for-Implementation-of-Mu
- Paper on FPGA-based-for-Implementation-of-Multi-Serials-to-Ethernet-Gateway