资源列表
ZIDONGDIANTIKONGZHI
- 三层的电梯控制,具备显示，加速，以及开关门的延时等操作-Three elevator control, including a display, acceleration, and an operation switch gate delay and other
16_buzzer
- verilog语言，fpga学习源码,初学者易懂-verilog language, fpga learning source, beginners to understand
22_sos_system
- fpga源码，供初学者使用，sos编码原理-fpga source code, for beginners, sos coding theory
24_lcd_gui
- fpga源码，供初学者使用，GUI系统说明-fpga source code, for beginners, GUI System Descr iption
Experiment01
- FPGA源码，初学者使用，时序程序分析，整数乘法器-FPGA source code, for beginners to use, timing program analysis，Integer multiplier
Experiment08
- FPGA源码，供初学者使用，时钟化和信号长度-GA source code, for beginners, clock and signal length
Exelixis-RRDR-2011-4
- IEEE Paper on Ethernet A Versatile UDP/IP based PC$FPGA Communication Platform -IEEE Paper on Ethernet A Versatile UDP/IP based PC$FPGA Communication Platform
udpip_literature
- Paper on UDP An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity -Paper on UDP An analysis of FPGA-based UDP/IP stack parallelism for embedded Ethernet connectivity
Count_1sec
- 使用FPGA下載達成計數一秒鐘功能 以測試完成可以使用 -Use FPGA download count reached a second function can be used to test complete
zhuangtaiji
- 状态机 多种状态的转换 verilog语言编写-Convert verilog language write state machine multiple states
half_adder
- VHDL code for generating half adder
shift_right
- VHDL code for generaring shift register