资源列表
FIFO
- 先入先出FIFO，用QUARTUS进行仿真-FIFO FIFO, the simulation with QUARTUS
counter8
- VHDL 8bit counter 可以进行8bit 计算，有fast slow两种模式-VHDL 8bit counter can be 8bit value, there are two modes of fast slow
FSM2
- vhdl final state mashine 售货机-vhdl final state mashine vending machine
tests
- test circuit about VHDL 测试程序 可运行-test circuit about VHDL test program can be run
counterFastSlow
- 完整vhdl计数器，多种功能。 stop/ en/ fast/ slow/-Complete vhdl counter, a variety of functions. stop/en/fast/slow /
vhd_SDH
- 实现从连续传输的SDH字节流中找出帧头、提取F1字节，并按照64K速率分别串行输出F1码流及时钟，其中64K时钟要求基本均匀。文件包含报告文档-SDH transmission from a continuous stream of bytes to identify header, extract F1 bytes, respectively, in accordance with 64K-rate serial output bit stream and clock F1, of which
usb
- contains important information about usb
WORKS
- Project of Adquisition Data, show in VGA and send to usb host
Verilog-Hdl_Circuit_Design
- Verilog-Hdl Circuit Design 电路设计-Verilog-Hdl Circuit Design
fpga2
- 正在学习FPGA, 这些资料跟大家分享一下.-Are learning FPGA, such information to share with you.
fpga3
- 正在学习FPGA, 这些资料跟大家分享一下.-Are learning FPGA, such information to share with you.
fpga4
- 正在学习FPGA, 这些资料跟大家分享一下.-Are learning FPGA, such information to share with you.