资源列表
DDR2_3(codePdoc)
- DDR2/3控制器的IP核及详细说明文档-DDR2/3 controller IP core and detailed documentation
fpga2dsp
- Altera Stratix II FPGA与TS201 DSP通过链路口通信的程序-Altera Stratix II FPGA and TS201 DSP through a chain junction communication procedures
fpga_ver
- Altera StratixII FPGA与DSP TS201实现总线通信的程序，Verilog实现-Altera StratixII FPGA and DSP TS201 implement the bus communication procedures, Verilog realization
How-to-write-state-machine
- 怎样写好状态机，很有启示的一篇文章,看了感觉不错-How to write state machine, very enlightening article
AD9648_ver
- FPGA通过SPI总线配置AD采集芯片AD9648的程序，Verilog实现 -FPGA configuration via SPI bus chip AD9648 AD acquisition procedures, Verilog realization
USB_fpga
- FPGA与USB PHY芯片Cy7c68013A通信的程序，Verilog语言-FPGA and USB PHY chip Cy7c68013A communication procedures, Verilog language
简单智能车VHDL实现
- FPGA实现智能车利用红外传感器使小车沿预定轨道平稳行驶，数码管显示障碍物与小车的距离，距离低于某值则停止运行
LPC-program-CPLD
- 使用quartus开发。该程序通过VHDL语言实现了LPC时序。控制了2个LED数码管，通过读取LPC总线的上BIOS的数据，实现了计算机排故的POST卡功能。-Use quartus development. The program through the VHDL language to achieve a LPC timing. Control of the two LED digital tube, by reading the BIOS on the LPC bus data to a
code1
- 实现50MHz时钟分频，点亮fpga开发板的led灯，并且让数码管动态显示电子计时-Implementation of 50MHz clock frequency, the LED lights FPGA development board, and make digital tube dynamic display of electronic timing
keyscan
- 利用VHDL语言编写的4*4键盘扫描程序，经过测试，可以放心使用。-Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.
verilog_VGA_ctrl
- verilog实现的VGA显示，Altera平台直接使用。程序简明。-verilog to achieve the VGA display , Altera platform directly. Program simple
counter
- 计算器的verilog语言程序代码。能实现加、减、乘、除运算。-verilog language of counter。it can achiev plus o, minus, multiplication and addition operations