资源列表
problemas
- example of vhdl lenguage-example of vhdl lenguage
vc707-mig-rdf0160-14.3
- 适用于DDR3 控制器代码等的FPGA代码-DDR3 controller code for FPGA code, etc.
Project
- Arithmatic logic unit
Projec2
- Delay Generator using VHDL
axi4-checker
- ARM公司官方的AXI4总线的SVA检测。带完整说明文档，AXI4，AXI4-Lite，AXI4-Stream协议均已经包含-ARM s official AXI4 bus SVA testing. With complete documentation, AXI4, AXI4-Lite, AXI4-Stream protocol are already included
DE2_labs_verilog
- This the code writing on verilog-This is the code writing on verilog
ColorBar
- verilog 视频领域 黑场信号产生-verilog field of video black burst signal is generated
axi3-checker
- ARM公司官方的AXI3总线的SVA检测。带完整说明文档-ARM s official AXI3 bus SVA testing. With complete documentation
jipin
- fpga检测输入信号的频率数码管显示可以检测到0HZ-20MHZ的输入频率。包括顶层代码，数码管显示代码，时钟分频代码。-fpga detects the input signal frequency digital display can detect 0HZ-20MHZ input frequency. Including top-level code, digital display code, clock divider code.
m_xulie
- 在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。-In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.
RS232_R_T
- 基于FPGA的verilog语言的串口通讯的数据接收和发送模块的程序-The data receiving and sending module of FPGA serial communication program based on Verilog language.
fpga-spi-to-uart
- FPGA的SPI转多路UART / 485-spi to uart or 485