资源列表
AD_DF_DA
- FIR滤波代码，先是AD的控制，后面是滤波的代码，系数通过matlab生成-FIR filter
test_sdram
- 原创的altera de2-70 FPGA板功能测试实验，用于SDram的读写。包含完整源代码，仿真文件，可直接下载到板子上的SOF文件，适合初学者研习。-Original altera de2-70 FPGA board function test, used for SDram read and write. Contains the complete source code, the simulation files, can be directly downloaded to the b
test_spi
- 原创的altera de2-70 FPGA板功能测试实验，用于spi的读写。包含完整源代码，仿真文件，可直接下载到板子上的SOF文件，适合初学者研习。-Original altera de2-70 FPGA board function test, used for SDram read and write. Contains the complete source code, the simulation files, can be directly downloaded to the boa
test_uart
- 原创的altera de2-70 FPGA板功能测试实验，用于UART的读写。包含完整源代码，仿真文件，可直接下载到板子上的SOF文件，适合初学者研习。-Original altera de2-70 FPGA board function test, used for UART read and write. Contains the complete source code, the simulation files, can be directly downloaded to the boa
test_vga
- 原创的altera de2-70 FPGA板功能测试实验，用于VGA的读写。包含完整源代码，仿真文件，可直接下载到板子上的SOF文件，适合初学者研习。-Original altera de2-70 FPGA board function test, used for VGA read and write. Contains the complete source code, the simulation files, can be directly downloaded to the board
bluespec-h264_latest.tar
- H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
dvb_s2_ldpc_decoder_latest.tar
- 用于数字电视机顶盒的DVB-S2的LDPC编码的解码模块，verilog代码-For digital TV set-top boxes of DVB- S2 LDPC coding, decoding module of verilog code
verilog_prj_seq
- 序列检测器，检测序列“11010”，verilog HDL代码。-Sequence detector, detection sequence "11010", verilog HDL code.
SDRAM_Test5
- 基于EP1C12Q240C8的红色飓风二代FPGA开发板的SDRAM测试程序，含有写入和读出FIFO，串口UART,数据发生模块。-Based EP1C12Q240C8 a red hurricane II FPGA development board SDRAM test program, containing written and read FIFO, serial UART, data generation module.
led2
- 流水灯，实现了简单的花样变化，便于初级学习使用-Light water to achieve a simple change in the pattern, easy to learn to use primary
cpld_uart_TXRX
- max2 cpld 开发的vhdl 完整串口通信程序，TXRX可同时收两个命令 带超时 600门-max2 cpld vhdl developed complete serial communication program, TXRX can simultaneously receive two commands with timeout 600
uart
- 基于FPGA的UART程序设计，VERILOG HDL语言编写，可实现串口通信，波特率为115200。已通过串口调试助手验证。-FPGA-based UART program design, VERILOG HDL language, enabling serial communication baud rate to 115200. Has been verified through the serial debugging assistant.