资源列表
ug_rsii
- Reed-Solomon II MegaCore Function user guide，altera的RS II编解码的宏功能模块的用户手册，是RS的升级版的IP，但大体使用一样。-Reed-Solomon II MegaCore Function user guide, altera s RS II codec macro function module user manual is an upgraded version of the RS s IP, but generally use
m7000
- ALTERA MAX EPM7000 series CPLD full datasheet
CycloneII-VerilogV
- Altra CyloneII Verilog文件，共有18个工程，包括标准键盘、串口、VGA、EEPROM、LCD1602等操作源码-Altra CyloneII Verilog files,include keyboar.com.VGA、EEPROM、LCD1602 operation surce codes
RCQ208_V3_24TFT
- Quartus NIOS例程，控制320*240TFT液晶显示，包括汉字、字符显示及显示缓存SDRAM控制驱动-Quartus NIOS routines, control 320* 240TFT LCD, including Chinese characters, character display and display control drive cache SDRAM
emifa_ram
- FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序-FPGA and DSP EMIF communication
ReactionTimer
- Reaction Timer verilog code, can be downloaded on texas NEXYS2 or NEXYS3 board to test the reaction time by pressing the buttons.
FIFO
- This a simple example of FIFO(first in and first out) module written in verilog code-This is a simple example of FIFO (first in and first out) module written in verilog code
PNgenerator
- This is a simple example of PNgenerator which use the clock signal inside the NEXYS3 board.This is basically a 8-bit PN number added by 256. The initial value cannot be all zeroes.
Binary_to_BCD_Converter
- This is a binary to BCD convert designed by using the “shift and add-3 algorithm”. The verilog code of basic cell add-3 is also included in this file.
StopWatch
- This a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.-This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
Counter
- Counter in VHDL using Xilinx ISE
seg7_driver
- verilog七段数码管驱动，显示内容可以自己更改。-verilog segment digital tube driver