资源列表
MFSK-VHDL
- 基于VHDL硬件描述语言，完成对基带信号的MFSK调制-Based on the VHDL hardware descr iption language, complete baseband signal MFSK modulation
motor-VHDL
- 步进电机定位控制系统，VHDL程序与仿真-Stepper motor positioning control system procedures and VHDL simulation
FSK-VHDL
- 基于VHDL硬件描述语言，对基带信号进行FSK调制-VHDL hardware descr iption language based on FSK modulation baseband signal
wtut_ver.ZIP
- 码表程序，完整的verilog工程文件，完整的工程设计流程，包含时序约束，ip核的嵌入，以及DCM模块的使用-Stopwatch program, complete verilog project file, complete engineering design process, including the timing constraints, ip nuclear embedding, as well as the use of DCM module
Verilog--Tutorial
- Verilog语言的入门教程，包含语言的结构，命令字符，标示符等语法的使用，以及各种入门的测试例程等。-Verilog language tutorial, including the structure of the language, the command character, identifiers etc. the use of grammar, and a variety of entry test routines.
CJQ-V1.0-fpga
- 实现FPGA对AD芯片AD7060的控制，程序代码的注释很多，易学易懂，适合初学者学习使用-it is good ...
UART_Trans
- 一个用来测试FPGA工作是否正常的程序，主要功能是串口数据的发送-An FPGA is working properly used to test the procedure, the main function is to transmit serial data
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
Altera_FPGA_CPLD
- Altera_FPGA_CPLD学习笔记 特权整理完善-Altera_FPGA_CPLD study notes privilege perfect finishing
Verilog-Template
- verilog 常用功能模块的实例，代码可以直接复制使用-verilog examples of commonly used function modules, the code can be directly copied using
ethernet.tar
- verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
ADDER16B
- 16位加法器,用于计算比较大的数据，希望对大家有帮助，多点下载，非常感-sixty bit adder