资源列表
divider8
- 这是一个8分频器，可以将输进来的信号进行8分频后输出-This is a 8 frequency divider which can transfer the input clock signal into 1/8 clock
divider256
- 这是一个2至256分频器，可以将输进来的信号进行2至256次分频后输出，分频器的大小可选-This is a 2 to 256 frequency divider which can transfer the input clock signal into 1/2 to 1/256 clock
ramIPcore
- 基于quartusII的ram调用，利用FPGA自身的blockram创立ram的ip core-Based on the ram quartusII calls itself blockram created using FPGA ram' s ip core
Virtex5user-guide
- VIRTEX用户文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX development must the Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
xilinx-forHDLDesigns
- VIRTEX原语库文件的中文文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX primitives library file Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
xilinx-forSchematicDesigns
- VIRTEX原理图原语库文件的中文文档，非常适合初学者和学习xilinx原语的同志学习-VIRTEX schematic primitives library file Chinese documents, very suitable for beginners to learn and learn from Comrade xilinx primitives
Xilinx-language
- 赛灵思术语词汇表，适合初学者学习研究使用，也可作为研究开发使用-Xilinx glossary of terms, suitable for beginners to learn research, can also be used as a research and development
FPGA_to_STM32
- FPGA与stm32进行通信的一个程序，串行通信-FPGA and a program to communicate stm32 serial communication
calc
- 一个简单的verilog计算器设计，键盘输入，数码管显示，实现加减与或运算-A simple calculator verilog design, keyboard input, digital display, Modified with OR operator
DDS_TLC5620
- DDS函数信号发生器 tlc5620 verilog-dds tlc5620 verilog
FPGA_CPU
- FPGA VERILOG CPU ASIC cpu芯片设计-FPGA VERILOG CPU
AD_TLC549
- verilog AD549 适合初学者 -verilog AD549