资源列表
uart protocol transmission
- todays data trans mission consist of more secured and low power with redused cost in technique well for that here is universel asyncronous reciever and transmitter with some protocol which make it to be secured
uart transmission rtl level
- UART transmission rtl level
cordic
- verilog实现的cordic算法，很好的代码，实际项目中使用过的。-verilog cordic
count
- 16位加法计数器，实现计数分频功能。时钟信号变化时，进行计数功能。-six accumulate
alpha_func
- This alphabet generating program in vhdl with various colors and models, i remodelled the oscillator to do this. maybe it will just for fun.-This is alphabet generating program in vhdl with various colors and models, i remodelled the oscillator to do
bianmaqi_count
- 光电编码器计数功能，光电编码器输出为一组差分信号-Photoelectric encoder counting function, photoelectric encoder output is a set of differential signal
cepin
- 采用等精度测频原理实现较宽范围内频率的测量-With equal precision frequency measurement principle to achieve a wide range of frequency measurements
jkff.vhd.txt
- JK FLIT-FLOPbianyi jian dan li ti
song_1
- 乐音控制按钮，可以控制音乐，通过按键音，中音。-Musical tone control buttons, you can control the music through the key tone, tenor.
lock
- 本设计 一个4 位数字锁，并验证其操作。 1、基本功能： （1 ）开锁密码为 4 位十进制数，通过按钮输入密码，输入的密码在4个数码管上显示，若与锁内预置的密码一致，输出开锁信号（以点亮一个LED灯表示开锁）。 （2）按钮开关输入须消抖处理。 2、扩展功能： 用户可以设置锁内的密码； 若输入密码三次不正确，输出报警信号，报警信号可以通过闪烁LED或某个数码管上小数点指示。 设置一个复位按键，忘记密码后可通过该复位按键恢复出厂原
seconds-counter
- 在EP2C5T144C8开发板上编的一个VHDL源程序，相当于一个秒表，读数可在4个数码管上显示，通过按键可暂停计数，可继续计数-In EP2C5T144C8 development board this a VHDL source code, the equivalent of a stopwatch, reading on the four digital tube display, can suspend count by buttons, can continue to count
FPGA--EP2C5T144C8
- EP2C5T144C8开发板资料，包括原理图，PCB图和USB驱动教程-EP2C5T144C8 development board materials, including schematic diagram and PCB diagram and the course of the USB drive