资源列表
verilog-codes
- xor code in verilog. can be used for fpga developement
fulladd4
- 全加器代码和测试激励文件，优化的全加器，占用FPGA资源少-Full adder code and test incentives
trafic
- traffic.v&test stimulas ,traffic control system
ddr_ram
- ddr_ram, ddr 工程调试文件，和测试向量激励-ddr_ram, ddr engineering code and test incentives document
ssl_decompose
- SSL安全协议解码源代码，和测试激励文件-SSL security protocol decoder source code, and test incentives document
pine_line_adder8
- 8 位全加器的设计，采用多pipeline设计方法-8 full adder multi-pipeline design
zigeti
- 基于FPGA的verilog语言写的按键控制步进1 的输出占空比从1 到99 的脉冲波，并用两位数码管显示出脉冲波占空比，按键key10加1 ,按键key11减1 。-FPGA-based verilog language button control stepper output duty cycle of 1 from 1 to 99 of the pulse wave, and use two digital tube display pulse duty cycle, key ke
FPGA-TOOL-chipscope
- FPGA的仿真工具chipscope pro的使用方法-FPGA simulation tools to use chipscope pro
pingball
- 用verilog写得弹珠小游戏，在BASYS平台上运行的-Pinball game with verilog written, running on a platform in BASYS
数字下变频FPGA 程序
- 数字下变频程序，完整的程序编译文件，适应于雷达信号处理，从ADC直接下变频
mac21
- this file is a multiply and accumulate logic built in VHDL platform.-this file is a multiply and accumulate logic built in VHDL platform.
fifo—VHDL
- good use of fifo first in first out