资源列表
vga_module
- VGA 显示源码。基于xilinx virtex ii 开发板开发。实现单色显示功能。-VGA display
am
- 基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.-Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the butt
VHDL-based-digital-clock-programming
- 基于VHDL的数字时钟设计，可以调时间，并且可以设置四个闹钟时间，中和很多VHDL的基本程序，对初学者很有用-VHDL-based digital clock design, you can adjust the time, and you can set four alarm time, and in a lot of VHDL basic procedures, useful for beginners
fenpin
- 对主时钟的完成四分频的分频，希望对大家有帮助。-Completion of the master clock frequency divider quarter, we want to help.
iic
- 主要对Iic通信协议做简单的规定，通过verilog语言设置。-Iic main communications protocol for doing simple rules, through verilog language settings.
ps2
- 使用verilog来对ps2的解码，使大家对ps2更好的理解。-Use verilog to decode for ps2, ps2 make everyone a better understanding.
chuankou
- 。典型的RS232 信号在正负电平之间摆动，在发送数 据时，发送端驱动器输出正电平在+5～+15V，负电平在-5～-15V 电平。接收器典型的工作电 平在+3～+12V 与-3～-12V 之间。-. Typical RS232 signal level swing between positive and negative, when data is transmitted, the transmitter side driver outputs a positive level in+
vga
- 该工程设计需要在VGA 显示器上显示背景为蓝色，中央显示一个绿色的边框和一个粉 色的矩形-The project design requires a VGA monitor to display a blue background, the central display a green border and a pink rectangle
shumaguan
- 该实验实现一个两位数码管同时从0 到F 循环递增的功能。-The experimental realization of a two digital tube while loop increments from 0 to F function.
mux16
- 在该实验中就是要利用时序逻辑设计方法来设计一个16 位乘法器-In this experiment is to use sequential logic design method to design a 16-bit multiplier
sram
- 该实验实现了对SRAM 的每一个地址进行遍历读写操作，然后比对读写前后的数据是否 正确，最后通过一个LED 灯的亮灭进行指示-The experimental realization of the SRAM to traverse each address read and write operations, and then compared before and after the data is read Correct, and finally through an LED fo
divider13
- 这是一个13分频器，可以进输进来的信号进行13分频后输出-This is a 13 frequency divider which can transfer the input clock signal into a 1/13 clock signal.