资源列表
vender1
- Vending Machine Controller Verilog Source Code
DDR2_Control
- 本文档以Siga-S16 Spartan 6的FPGA开发板为例，为大家介绍用MIG工具生成DDR2控制器，并用ChipScope调试DDR2读写的方法。 -This document in the FPGA development board Siga-S16 Spartan 6 as an example, to introduce the formation of DDR2 controller with the MIG tool, and use the debug method of
hello_audio
- 通过本篇，您可以了解到MicorBlaze系统通过I2C接口控制语音芯片WM8731的方法及通 过I2S的接口和WM8731的数据通信实现录音和播放的功能。-Through this article, you can realize the control of MicorBlaze system voice chip WM8731 through the I2C interface and realized through I2S data communication interface
DES
- Data Encryption Standard(DES) VHDL Source Code
vga
- VGA graphic controller Verilog Source Code
18_uart
- FPGA串口通信，可以实现高速通讯，具有良好的模块说明-FPGA serial communication
uart_Verilog
- uart接口verilog源码，实现数据串并行的转换。内容包含十个代码文件。-uart Interface verilog source of data for serial-parallel conversion. Contains ten code files.
UART verilog代码
- UART verilog代码，基于时间单位为1ns，精度为100ps的UART代码
SPI-masterslave
- SIP-serial peripheral interface one type of serial communication bus protocol for network environment
Stamp-vending-machines
- 设投币初始状态为ST0，如果投入一枚五毛硬币为ST1, 如果投入两枚五毛或者投入一枚一元硬币（累计一元）为ST2，如果投入三枚五毛或者一枚五毛和一枚一元（累计一元五角）为ST3，如果投入四枚五毛或者两枚五毛和一枚一元或者两枚一元（累计两元）为ST4，在ST4状态下，如果再次投入一枚五毛硬币，则输出邮票并返回初始状态，如果再次投入一枚一元硬币，则输出邮票并找回五毛同时返回初始状态。-Stamp vending machines
zhuangtaiji
- 状态机实现，通过简单的程序实现状态机，让你最快的掌握用VERIlog语言写的状态机-State machine implementation, through a simple procedure to implement state machines, allowing you the fastest master the language used to write state machine VERIlog
I2C
- 基于FPGA的I2C通信代码实现，在开发板上验证过，欢迎使用-FPGA-based I2C communication code, tested on the development board, welcome