资源列表
ARITHMETIC
- 算术乘法器，这是我自己设计的算术乘法器，是用VHDL语言设计的，希望对大家有帮助-Arithmetic multiplier, this is my own design arithmetic multiplier, is designed with VHDL language, and they hope to help everyone
EX16
- verilog 一个小程序 关于DS18B20 的驱动程序-verilog a small program on DS18B20 driver
police_siren
- 警察车的声音，利用verilog编写，可以下载到PFGA，已经在altera cycloneIII芯片上验证成功-The sound of the police car, use verilog to write, can be downloaded to PFGA, has proved to be successful on the chip altera cycloneIII
freq_viewer
- quartusii下基于原理图方式构建的频率计，在altera cyloneIII 芯片上已经验证成功，精度为1Hz-quartusii under way to build a schematic-based frequency meter, in altera cyloneIII chip has proved to be successful, the accuracy of 1Hz
vhdl-programs
- vhdl source codes for various digital systems
fft
- FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。-FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.
IIC_EEPROM
- IIC_EEPROM是通过IIC传输方式与EEPROM金星数据传输的Verilog工程原文件。-IIC_EEPROM by IIC transmission of data transfer with EEPROM Venus Verilog project the original file.
multiplier
- 乘法器的verilog工程文件，可以进行仿真实验，有详细解释，适合初学者学习参考。-Multiplier verilog project file, can be simulated, with detailed explanations, suitable for beginners to learn.
root_cordic
- 这是求平方根的VHDL工程，使用CORDIC旋转坐标算法，完整的工程文档，可以仿真实验。-This is the square root of the VHDL project using rotating coordinate CORDIC algorithm, a complete engineering documents, can be simulated experiments.
DCT
- Discrete Cosign Transform(DCT) Verilog Source Code
JPEG
- JPEG Encoder Verilog Source Code
random_num_gen
- Combination is formed by permuting and XORing 32 bits of LFSR and CASR