资源列表
pingpongf16
- 使用quartusii软件,用verilog语言编写，通过DE2-70板在屏幕上实现乒乓球动态效果。-Use quartusii software, using verilog language, through the DE2-70 board on the screen to achieve tennis dynamic effects.
tequan
- 特权同学 深入浅出玩转FPGA视频教程里面的verilog代码-Fun privileged classmates easy video tutorials inside FPGA verilog code
lab-1
- Lab1 from altera this is basic is getting to you
lab-1.2
- this is lab2 from altera
lab-1.3
- thisi s lab3 from altera
cpu_store
- VHDL语言制作CPU，8位，16条指令，能够完成多种操作. -VHDL language production CPU, 8-bit, 16 instruction, to complete a variety of operations. VHDL language with CPU, 8-bit, 16 instruction, to complete a variety of operations.
FPGA
- verilog编写的QPSK发射机的ＦＰＧＡ部分，已经过验证，完全达到要求。调制矢量误差４％-QPSK transmitter verilog prepared by the FPGA portion, has been proven, fully meet the requirements. Modulation vector error of 4
CPU_z
- 上计算机组成原理课时，老师提供给我们的简单8位CPU。-On computer organization class, the teacher give us a simple 8 CPU.
Verilog_COMPLEXCLOCK-v2013.10.07
- 电子钟，闹钟，秒表，可调时间，采用6位数码管显示-Electronic clock, alarm clock, stopwatch, adjustable time, the use of six digital tube display
Verilog_CLOCK-v2013.10.07
- 六位数码管显示的电子钟，可以调整时间，通过验证-Six digital display electronic clock, you can adjust the time by verifying
CPLD_LCD
- 用verilog编写的1602显示屏的程序，通用性较强，测试平台是DE0-Written in verilog 1602 Display of the program, versatility is strong, the test platform is DE0
ads805
- 电设用到！用verilog编写的TI的ADS805的调试程序。测试平台是DE0 。-Electric facilities used! TI' s written in verilog ADS805 debugger. Test platform is DE0.