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  1. clock

    0下载:
  2. 电子闹钟,实现了基本的计时功能,此外还能设定闹表时间。-Electronic alarm clock to achieve the basic timing functions, in addition to also set the alarm clock time.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:173.11kb
    • 提供者:龙一
  1. Desktop

    0下载:
  2. 四选一多路选择器 modelsim testbench-Select more than one four-way selector modelsim testbench
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:92.96kb
    • 提供者:
  1. counter

    0下载:
  2. 此代码是一个小的计数器,主要驱动FPGA开发板上的LED灯的亮灭。-This code is a small counter, the main driver FPGA development board bright LED lights eliminate.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:152.38kb
    • 提供者:左朋莎
  1. arlut_fifo_interface

    0下载:
  2. fifo控制器,可以加到nios系统下,通过nios进行FIFO的读写,经过本人的项目验证-fifo controller, can be added to the nios system, through the nios to FIFO read and write, after I verified the project
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:15.89kb
    • 提供者:11
  1. ISE9.1user_guide

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  2. ISE9.1 user guide ISE开发环境使用指南-ISE9.1 user guide
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-16
    • 文件大小:4.11mb
    • 提供者:ariesl
  1. veriloghdl-tutorial-135-cases

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  2. veriloghdl教程135例,包含很多基础代码,可以用于学习,或者扩展为其他应用-veriloghdl tutorial 135 cases, including a lot of infrastructure code that can be used to study, or extended to other applications
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:162.9kb
    • 提供者:zhanghailong
  1. UARTipcore

    0下载:
  2. 这是一个关于UART的IP核,用VHDL写的。经过本人的鉴证,非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:21.76kb
    • 提供者:11
  1. daima

    0下载:
  2. 关于《无线通信FPGA设计》的源代码,有matlab和fpga的实现,非常好,特别是对于做信号处理的。-On " Wireless Communications FPGA design" of the source code, there is matlab and fpga implementation, very good, especially for doing signal processing.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:204.92kb
    • 提供者:11
  1. Leds

    0下载:
  2. Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:364.17kb
    • 提供者:xanflixus
  1. TheDesignersGuidetoVHDLVolume3

    0下载:
  2. VHDL, the IEEE standard hardware descr iption language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. Th
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.66mb
    • 提供者:AWAIS
  1. VHDL2008JusttheNewStuff

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  2. VHDL2008 Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware descr iption language. Written by the Chair and Technical Editor of the IEEE working group, the book i
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2016-06-02
    • 文件大小:782.6kb
    • 提供者:AWAIS
  1. DesignrecepiesforFPGAs

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  2. This book provides a rich toolbox of design techniques and templates to solve practical, everyday problems using FPGAs. Using a modular structure, the book gives easy-to-find design techniques and templates at all levels. together with functional cod
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-04
    • 文件大小:1.31mb
    • 提供者:AWAIS
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