资源列表
VerilogLabSource
- Verilog Lab Source Codes
15freeIPcore
- 15个免费的IP核 FPGA开发助手,-15 free IP core FPGA Development
DE2_schematics
- DE2 sch -DE2 sch .............
count
- 实现各种计数器的vhdl的实现方法,经过验证-many count
UART
- 实现异步串口,异步串口的收发.已经通过验证.-UART
Q
- 制作一个锁存器,常用于地址的所存,上升沿触发-DtoQ
more
- more状态机.有自起动,功能.出错自检,通过验证-more state
DE1_SD_Card_Audio
- DE1 Sopc SD card audio
MAXII
- MAX II EPM7000 系列 FPGA CPLD 芯片的使用手册,仅供参考,-MAX II EPM7000 Series FPGA CPLD chip user manual for reference purposes only
i2c
- verilog hdl file i2c interfacing-verilog hdl file i2c interfacing
ff
- 在DSP BUILDER上实现数字滤波器-In the realization of digital filters on a DSP BUILDER
cpu25
- 8 bit cpu code using vhdl it performs various operations
