资源列表
sdr_sdram_epm570
- CPLD芯片EPM570对SDRAM的读写操作，通过串口显示。-SDRAM write and read test based on CPLD chip-- EPM570.
SPCQF
- 8路抢答器的设计，程序采用verilogHDL语言编写-8-way Responder design, the program uses language verilogHDL
cossin
- 数字信号源，输出不同频率，相位的正余弦信号，-Digital signal source, the output of different frequency, phase is the cosine signal,
cic_cz
- 在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co
mulbinarytree
- 16位二叉树乘法器（阵列乘法器），VHDL实现-16-bit binary tree multiplier (array multiplier), VHDL realization
_4to2
- 基于verilog编写的4线2线编码器，在板子上直接运行，相应引脚自己配置-Verilog prepared based 2-wire 4-wire encoders, running directly on the board, the corresponding pin their allocation
CD1_OV5620_DISPALY
- 基于FPGA的CMOS图像传感器（OV5620）显示图像-FPGA-based CMOS image sensor (OV5620) image
Design-Space-Exploration-of-Hard-Decision-Viterbi
- Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation
TS_i2c
- 基于xilinx spartan 3e 开发板的CAT34TS02 AT30TSE002B 等 带有温度传感器EEPROM 的TS 部分测试程序。通过串口写入数据和地址。按键控制从串口读出内部寄存器值，同时LCD予以16进制显示。 本人编写亲测。-Based on the xilinx spartan 3e development boards CAT34TS02 AT30TSE002B TS part of the test program with a temperature senso
verilogPPT
- verilog基本语法，便于查询和使用，是学习verilog不可或缺的语法书，便于记忆，使用方便-verilog basic syntax, ease of access to and use is essential to learn verilog grammar book, easy to remember, easy to use
fulladder
- Simple four bit full adder using concatenation in VHDL.
DDS_100325(13)_success
- QUARTUS II环境下VHDL语言编写DDS程序，双数字信号输出，一为正弦波幅值输出，一正弦波差值信号。时钟2^21HZ，带24bits频率控制字。-QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bi