资源列表
iicmax
- verilog 利用i2c对24c08进行读写-the verilog make use of i2c 24c08 read and write
timer
- 在NIOS IDE开发环境下实现对定时器的编程，适合新手入门使用-In NIOS IDE development environment to achieve the timer programming, suitable for beginners to use
TRDB_LTM_UserGuide_v1.23
- TRDB_LTM使用说明书，用户手册，LTM的一些说明-TRDB_LTM manuals, user manuals, LTM some of the instructions
fifo_exp1
- 在ISE环境下用VHDL写的8*9FIFO
VHDL-Programming-Examples
- 分频器、译码器、编码器、计数器、状态机等基本的硬件描述语言代码-The basic hardware divider, decoders, encoders, counters, state machine descr iption language code
ug_cpri
- cpri altera ip core用户手册，一看就能够清楚的-cpri altera ip core manual, one can clearly see
snake
- 用VHDL语言编写的贪吃蛇小游戏。利用有限状态机原理，对不同情况判断得到下一步操作参数。程序下载能够运行-VHDL language with the Snake game. Finite state machine theory, judging by the different operating parameters for the next step. Download to run
music
- 功能描述：向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调，该实验通过设计一个状态机和分频器使蜂鸣器发出"多来咪发梭拉西多"的音调。（VHDL）-Function Descr iption: to the buzzer to send a certain frequency square wave can make the appropriate buzzer tone, the experiment by designing a state machine and the divider
FA_pow
- Power estimation of full adder including SAF and VCD file
st7565r
- ST7565R 驱动65 x 132 Matrix LCD 中文版（内含相关寄存器中文注释及初始化步骤）-ST7565R 65 x 132 Dot Matrix LCD Controller/Driver
qdq
- 用VHDL语言实现四路抢答器功能，抢答之后不能再抢答，除非主持人按下复位键。可以显示四个选手分数，显示答题倒计时的时间，主持人可以控制加减分，分数通过显示屏显示。使用软件Quartus Ⅱ，可以将程序导入FPGA并能运行。有竞争模块，显示模块，分频模块，加减控制模块，计数器模块，蜂鸣器模块，译码模块，计分器模块，锁定模块等。-VHDL language with four Responder function can not answer after answer, unless the hos
Chapter9-Sample
- FPGA实现CAN通信，经过验证，并可以仿真-FPGA Implementation of CAN communication, proven, and can be simulated