资源列表
Exp8-GAME
- FPGA小游戏，代码内部说明清晰，可自习斟酌-FPGA game, code clarity of internal notes, as appropriate, to study
verilog
- Verilog学习例程：4位二进制数的乘法器、5分频器、8位数据寄存器、8位移位寄存器、边沿D触发起门级设计、边沿D触发器行为级设计、同步计数器、异步计数器-Verilog learning routines: 4-bit binary number multiplier, 5 dividers, 8-bit data registers, 8-bit shift register, edge-triggered D gate-level design, level design edge D
jisuanqi
- 用VHDL语言实现通用计算器设计，MUXPLUS2软件仿真验证-Implementation using VHDL language design generic calculator, MUXPLUS2 software simulation to verify
ICC_
- 用FPGA实现了对IIC器件AT24C02的读写操作。系统上电后先读取AT24C02内部的数据，然后不断写入改变的新数据，数据的变化显示在数码管上。-The operation of reading and writing the IIC device AT24C02 by FPGA has been come true.When the system powered on FPGA reads the internal data of AT24C02,and then write the ch
dds
- 一个可用的很不错的DDS 频率合成程序，用VHDL语言编写-Available is a good DDS frequency synthesis procedures, using VHDL language
.tranfervw
- 一款可以生成.vwf的小软件 对编写verilog语言很有用-a software for vwf file of verilog code programming
multiply_shift_add
- 基于移位相加运算的乘法器设计，multiply_shift_add中包含了完整的设计工程文件，可在Xilinx ISE中运行-Adding operation based on shift on time-multiplier design, multiply_shift_add contains the complete design engineering documents, Xilinx ISE in running
shizhong
- 在Quartus II 环境下利用Verilog语言编写的时钟程序，包含模块化器件和仿真波形-In the Quartus II environment, use Verilog language clock procedures, including modular devices and simulation waveforms
digitalsystemdesign
- 非常经典的FPGA设计PPT，北航夏宇闻老师讲义-FPGA designs are very classic PPT, Beihang XIA Yu-Wen teacher handouts
jibenrenwu1
- 一个用vhdl语言写的简单输出正弦波的程序，适用于初学者-Vhdl language used to write a simple sine wave output of the program, for beginners
testRAMWR
- 这是一个用VHDL编写的读写双口RAM的程序.-This is a work written in VHDL to read and write dual-port RAM program.
pspice
- pspice软件教程，比较全面是电子仿真的最好选择-pspice software features introduced in more detail the contents of