资源列表
edacounter
- 用VHDL语言编写的计数器，在板子上运行成功，可以循环计数，加减计数，先置数后计数等-Counter with the VHDL language, in the board to run successfully, you can cycle counting, addition and subtraction counting, numbers, counting the first home
extension_pack_latest.tar
- This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code.
extension_pack_latest.tar
- This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code. Automatic count stop/start value generation functions. You enter a time duration and clock frequency and the v
MB_Labs
- example VHDL for spartan e3
CoG
- Semi-functional FSM and ROM for Xilinx CPLD to drive ST7565R based off Digikey example
MUXplus2
- Max+plusⅡ是Altera公司提供的FPGA/CPLD开发集成环境，Max+plusⅡ界面友好，使用便捷，被誉为业界最易用易学的EDA软件。本资源分七节内容详细的讲解了MUX+PLUSⅡ软件的操作及应用。-Altera Max+ plus Ⅱ is provided by FPGA/CPLD development integration environment, Max+ plus Ⅱ friendly interface and easy to use, known as the ED
ADS805FPGA 用FPGA来实现对ADS805的采用控制
- 用FPGA来实现对ADS805的采用控制，内部含有DDS程序-ADS805 with FPGA to achieve the adoption of control, internal procedures with DDS
Advanced-Digital-Design-with-the-Verilog-HDL-CODE.
- 《Verilog HDL高级数字系统设计》（Michael D. Ciletti著） Verilog HDL源代码-" Verilog HDL Advanced Digital System Design" (Michael D. Ciletti a) Verilog HDL source code
EDA-shuzizhong
- 用EDA软件实现数字时钟的设计，提供详细的代码-Using EDA software to realize the digital clock design, with detailed code
ddrct_gen_o4_1_008_1
- 有关ddr设计的控制问题，ddrct_gen_o4_1_008_1.zip 非常有用
vhd123
- 基于VHDL的实现赛车点阵，赛道和赛车，能够左右移动-VHDL-based matrix to achieve racing, track and racing, can move around
lab_cor_8
- cordic算法实现8次迭代计算sin(x)-8 iterations cordic algorithm computing sin (x)