资源列表
VHDLipinji2
- 此码基于FPGA开发环境用quartusII软件编写的一个未分模块的整体程序用于测量0-1000kz的频率-This code is based FPGA software development environment, written by quartusII a sub-module of the overall procedure is not used to measure the frequency of 0-1000kz
UART_FPGA
- 此vhdl程序实现了在FPGA上构建UART通信串口。分为两部分，UART的发送端transfer和接收端receiver。需要外部根据需求提供波特率时钟。-This program implements the building vhdl UART serial interface on the FPGA. Divided into two parts, UART transfer sender and receiver receiver. Required to provide the ba
ds1302
- 根据黑金动力编写的ds1302的vhdl程序，方便初学者对ds1302的学习-Ds1302 prepared according to the power of black gold vhdl procedures, easy for beginners to learn ds1302
miniuart_vhdl
- 用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware descr iption language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
aes_package
- This Module defines all the functions and Signals used at various instances in the algorithm in a package
aes
- 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
9.3_Pulse_Counter
- 基于Verilog-HDL的硬件电路的实现 9.3 脉冲计数与显示 9.3.1 脉冲计数器的工作原理 9.3.2 计数模块的设计与实现 9.3.3 parameter的使用方法 9.3.4 repeat循环语句的使用方法 9.3.5 系统函数$random的使用方法 9.3.6 脉冲计数器的Verilog-HDL描述 9.3.7 特定脉冲序列的发生 9.3.8 脉冲计数器的硬件实现 -based on V
s
- 2选1 选择器 寄存器 等源代码 希望对大家有用哈-2 Select a selector register code, etc. I hope useful for Kazakhstan
UART
- 自己写的RS232串口程序，波特率可调，调整在CLKUNIT文件中-RS232 serial port to write their own programs, the baud rate is adjustable, you can adjust it in the file of CLKUNIT
finBlockDiagram
- this a functional blosk diagram for a digital signal processor-this is a functional blosk diagram for a digital signal processor
wavegenerator_testbench
- 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
wendu
- 基于FPGA的温度源代码，赛林思比赛专用-Based on FPGA temperature the source code, and the "special LinSi game