资源列表
fulladder
- this is fulladder 1bit with testbench
divizor_fregventa
- contains a divider on the frequency that can be obtained at 13.5 MHz output if the input signal is applied to a 40 MHz
Four-digital-adder-count
- 该程序控制开发板上四位数码管进行加法计数，从0000至9999，溢出后清零-The program to control development board counts up four digital tube, cleared 0000-9999, after overflow
3-x-3-button-light-water
- 该程序控制开发板上led依次点亮，达到流水灯的效果-The program control development in turn led panel lights, to the effect of light water
led-and-digital-synchronous-beating
- verilog HDL语言程序，可以控制led和数码管同步跳动-verilog HDL language program, you can control led and digital synchronous beating
jiaotongdeng
- 十字路*通灯的控制，用fpga实现，verilog语言，可实现两个方向红绿黄左拐灯的控制。-Control crossroads traffic lights, with the fpga realize, verilog language, can achieve control of red, green and yellow in both directions left lamp.
edasingene
- 基于FPGA的正弦信号发生器的设计，用verilog语言实现，可调整频率和周期。-FPGA design based on sinusoidal signal generator with verilog language, adjust the frequency and period.
freq
- 基于FPGA的频率计，用verilog语言实现，在标准时钟周期内进行计数，得到信号的频率。-FPGA-based frequency meter, using verilog language, the standard clock counted to obtain the frequency of the signal.
local-bus
- 基于FPGA的local bus接口。包含基于fifo和普通寄存器的两种方案。-FPGA-based local bus interface. Based fifo contains two programs and the general register.
dds
- 这是自己写的dds源码，利用查找表方法，亲测可用。-It is written in their own dds source, using a lookup table method, pro-test available.
Booth2-multiplier
- 一个18bit乘以18bit的Booth2编码的乘法器，已验证通过-A 18bit*18bit booth2 mutiplixer
PipeLine-GCD-DSP
- 流水线结构的最大公约数处理器，处理的数据为32bit,采用64级流水线实现。-A pipeline sturcture GCD DAC, data width is 32bit.