资源列表
uart
- 通过CPLD，可以进行和电脑的串口通讯。-By CPLD, and computers can be serial communication.
paralleladder
- This a verilog source code for parallel adder-This is a verilog source code for parallel adder
barrelshifter
- Here is barrel shifter source code with verilog language
Counter1s
- counter number one to nine after 1s-counter number one to nine after 1s
FSM
- lap trinh FSM may trang thai
Decoder
- decoder 3 to 8 verilog
DieuKhienLed
- dieu khien led DE2-70
FullAdder
- full adder verilog de2-70
counter
- 基于Xilinix公司的BASYS2板子完成的一个计数器电路以及仿真代码。-Based on a counter circuit board Xilinix company BASYS2 completed and simulation code.
PWM
- 基于Avalon总线的PWM的实现，verlog语言编程-PWM-based Avalon bus implementations, verlog language programming
State-machine-design-techniques
- 状态机设计-英文-如何编写状态机-case-State machine design techniques for Verilog and VHDL
yuandongkz
- 案例 例1_单轴运动 例2_回原点运动 例3_直线插补例4_两轴圆弧插补例5_连续插补例6_手轮运动(VC)例7_通用专用输入输出