资源列表
DDS
- 主要现实FPGA中TLV5618模块，学习将模拟电流信号转化为数字信号，并且显示到数码管，本程序范围0-5V-TLV5618 major reality in the FPGA module, learning the analog current signal into a digital signal, and the digital display, the program range 0-5V
yudanpianjidechuankoutongxin
- 基于fpga的与单片机进行串口通信的vhdl程序-FPGA serial communication with the MCU VHDL program based on
versionOK
- 音乐魔方：对音频信号进行采集，通过FFT变换得到频谱信息，将频谱信息在LED阵列上显示。-Music Cube: an audio signal acquisition, spectral information obtained by FFT transform, the spectral information is displayed on the LED array.
aes
- contains AES doc with code in Verilog
spi1
- 使用verilog语言编写的实现cpld EPM570与EEPROM的SPI通信-Using verilog language to achieve cpld EPM570 SPI communication with the EEPROM
multifuctional-digital-clock
- 多功能数字钟，万年历，可显示时间，年月日，闹钟，功能十分强大，在DE0上通过-Multifunction digital clock, calendar, you can display the time, date, alarm clock, is very powerful in the DE0 by
clock
- 多功能数字钟，具有调时校时，整点报时，闹铃及其设定等功能，可直接下载到DE0开发板上-verilog clock
yz
- LCD字符控制显示器设计，显示学号和姓名-Character LCD control display design, student number and name display
top_FFT
- 128k点流水FFT算法的IP核设计，顶层文件，一共13级流水-128k-point FFT algorithm running water IP core design, top-level file, a total of 13 water
butterfly
- FFT模块里的蝶形运算单元，需要用到加法器，减法器，二选一选择器-FFT module of butterflies, need to use an adder, a subtracter, a second election selector
complexMul
- 复数乘法器，利用ISE里的float IP核，实现了32位复数的乘法-Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications
complexadder
- 32位复数加法器，利用ISE里的float IP核-32 complex adder, using the ISE in the float IP core