资源列表
display-circuit
- 计数显示电路 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Counter display circuit,simulation with Quartus 10.0+ modelsim 6.5SE， reports
detector-(1110010)
- 序列检测器（1110010）设计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE ， reports
VHDL-taxi
- 出租车计价器VHDL程序，有备注，适合初学者。-Taximeter VHDL procedures, suitable for beginners.
sencond_counter
- 在ise14.7开发环境下，用Verilog编写的秒表程序，其中通过状态机实现数码管的动态显示-In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
cnt
- 在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表-In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch
johnson
- 此代码实现约翰逊计数器，内容不多，注释详尽，供初学者使用。-Johnson counts
UART_Verilog
- uart接收模块，Vrilog编写，实现与PC机的同信-UART Receiver module
proj-ASC
- simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
traffic_light_3_09
- 数码管驱动、HC595驱动、VHDL、分频器-Digital tube drive, HC595 drive, VHDL, divider
I2C_Single_Master
- I2C Single master written in Verilog Libero Designer core generator.-I2C Single master written in Verilog Libero Designer core generator.
reed_solomon_decoder
- Reed Solomon Decoder written in Verilog Libero core generator.-Reed Solomon Decoder written in Verilog Libero core generator.
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.