资源列表
acc
- This code has function to accumulate
rrc
- This code implement rrc filter
addsub
- This code implement add or sub between 2 number
adder
- This code implement add between 2 number
cordic_base_j
- This code implement a interation in cordic pipelline
grantyz
- 4倍频鉴相功能模块，利用Verilog hdl语言编写的-4x phase function module using Verilog hdl language
divider
- 使用模为2N+1的计数器,让输出时钟在X-1(X在0到2N-1之间)和2N时各翻转一次,则可得到奇数分频器,但是占空比并不是50 -The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50
shiyan
- 使用FPGA设计的一种跑表，但只是用来实验上的仿真-FPGA design using a stopwatch, but only for simulation on
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
music.tar
- Verilog example of a program that plays some tones when connected to a speaker. Implemmented in FPGA Nexys3
displayCounter2.tar
- Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Implemmented in FPGA Nexys3-Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Imple
inputPinsTest.tar
- Verilog example of a program that test the input and outputs pins FPGA by making them 1 and 0 in a specific time. Implemmented in FPGA Nexys3-Verilog example of a program that test the input and outputs pins FPGA by making them 1 and 0 in a specific