资源列表
LL
- verilog语言的计数器设计程序代码。-counter verilog language design code.
water-lamp
- 这是关于流水灯的vhdl程序，功能是8个led灯间隔1s交替变亮-This is a light water vhdl program, 8 led light interval 1s alternately brighten
SDRAM
- 用XilinxSC1500控制SDRAM的一段VHDL代码。控制SDRAM每个时钟内输出地址所在的一个数据。-For some VHDL code with XilinxSC1500 Control SDRAM. Control SDRAM Each clock output address where a data.
MotorVHDL
- 一个关于松下伺服电机驱动及反馈的VHDL程序-VHDL program a Panasonic servo motor drive and feedback
FPGA-BASYS2
- 基于FPGA BASYS2开发板的数字钟，能够实现计时，时间校准，闹钟，整点报时等功能。-Development board based on FPGA BASYS2 digital clock, to achieve timing, time calibration, alarm, hourly chime functions.
i2c-master
- I2C Master Code in Verilog using Finite State Machine.
FPGA_BDPSK
- FPGA实验_BDPSK调制解调器设计(包含10个模块)-Experimental _BDPSK modem FPGA design (including 10 modules)
Random_Derandom
- 通信中加扰/解扰算法。FPGA源代码，verilogHDL语言实现，包含测试程序。-Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.
RFID_VERILOG_1988
- RFID Reader using verilog
multiplier_n_bits
- VHDL multiplier - input : two n (n customizable) bits width vectors
square_root_n_bits
- VHDL square root - compute square root n (n customizable) bits width vector (restoring square root algorithm)
bpsk
- 基于matlab的bpsk解调仿真，包括误码率的结果比较。- U57Fn