资源列表
systolic_mul_D8_M193
- 193位8段的GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-a 193bit GF(2m) Ditital-Serial Systolic Multiplier
LCD_Driver_better
- this a characteristic 16x2 LCD Driver by VHDL-this is a characteristic 16x2 LCD Driver by VHDL
plj
- 多功能频率计，可以测量10HZ到10MHZ的频率脉冲，精度为1赫兹，另外有计数器功能-Multifunctional frequency meter, you can measure the frequency of the pulse 10HZ to 10MHZ, and an accuracy of 1 Hz, and another counter function
module-display
- 数码管显示1234，通过调整开关决定数码管显示顺序为1234或4321.-Digital display 1234, by adjusting the switch determines the order of the digital display 1234 or 4321.
Exemple_1_Clock_24
- vhdl code for 24 clok with some options hope u will like it vhdl code for 24 clok with some options hope u will like it vhdl code for 24 clok with some options hope u will like it -vhdl code for 24 clok with some options hope u will like it
Exemple_2_VGA
- my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga-my vhdl code to intrface with a vga my vhdl code to intrface with a vg
First_test_Blinking_LEDs
- my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds -my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first
ucf-for-ML402
- ucf for mml402 and ise design software.-ucf for mml402.
flowing-water-light-code
- 这是一段基于DE2开发板的流水灯Verilog hdl 代码-This is a based on DE2 development board of flowing water light Verilog HDL code
FJ8030_fpga.out
- 一种关于FPGA系统设计的时钟约束文件，可以直接添加到主模块以减少Unconstraint path-A timing constraints on FPGA system design documents
VGA3gray
- 基于FPGA的显示器测试图像生成程序，开发平台基于DE2-115，红绿蓝三通道控制像素点的颜色。-FPGA-based image generation display test program, the development platform is based on DE2-115, red, green and blue color channel control pixel.
short_generator
- OFDM的短序列verilog语言，802.11a的标准-OFDM short sequence verilog language, 802.11a standard